搜索资源列表
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
fifo_design
- 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
FIFO
- here is realized simple FIFO stack in vhdl. very simple example, but very helpful.
FIFO
- fifo的实现，可以作用于memory的数据传输等地方，在fpga上实现，可以进行综合和仿真-fifo implementation, you can act on memory data transfer and other places, in the fpga to achieve, to undertake a comprehensive and Simulation
FIFO_32B
- This file is the implementation of a 32B FIFO in VHDL and can be implemented as Gate level. It was developed by ISE7.1
try_fifo
- An implementation of fifo in VHDL.
FIFO
- FIFO control in the FPGA-FIFO control in the FPGA
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
vhdl-ad9910
- ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
FIFO
- Quartus下VHDL编写的一个FIFO模块，调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
FIFO
- a fifo designed in vhdl. this fifo is implemented in a different way, using access type.
FIFO
- FIFO在VHDL上的实现。没有注释，较为完善，已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
fifo
- fifo buffer in vhdl, first in first out in vhdl, vhdl code
Asynchronous-FIFO
- Asynchronous FIFO Implementation in VHDL
fifo—VHDL
- good use of fifo first in first out
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
fifo_srl_uni
- asynchronous fifo in vhdl
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
fifo_control
- vivado project file for fifo in vhdl